On 3/24/2025, PCIe has undergone multiple iterations and upgrades since its inception, and has now become an indispensable interconnect bridge between computing devices such as CPUs, GPUs, FPGAs, SSDs, etc. The PCIe 7.0 standard has further increased the data transfer rate to an astonishing 32 GB/s (per channel), and recently PCI-SIG released version 0.9 of the PCI Express 7.0 specification. As expected, the official version of the SPEC specification will also be released within 2025, much earlier than the previously anticipated year of 2027. PCIe 7.0 will increase the data transfer speed of each pin to 128 GT/s, significantly improving PCIe 6.0's 64 GT/s and PCIe 5.0's 32 GT/s. This means that before considering encoding overhead, a 16 channel (x16) connection can support a bidirectional bandwidth of 512GB/s. In order to improve data transmission rate and bandwidth, the PCIe Gen7 interface will use four level pulse amplitude modulation (PAM4) signaling, 1b/1b flit mode encoding, and forward error correction (FEC), all of which are functions inherited from PCIe Gen6 in this standard. Although the final version of PCIe 7.0 specification is expected to be released within 2025, due to various obstacles encountered in research and development, testing, and manufacturing processes, actual products may take longer to be widely popularized.
Key Characteristic Indicators for PCIE7.0
1. Doubling bandwidth:
PCIe 7.0 aims to double the transmission rate of PCIe 6.0 (64 GT/s) to a raw bit rate of 128 GT/s, and provide up to 512 GB/s bidirectional transmission speed through x16 configuration. This represents a significant leap in data throughput, which is crucial for applications that require processing large amounts of data.
2. Adopting PAM4 signal technology:
Continue to use and optimize the Pulse Amplitude Modulation with 4 levels (PAM4) signal technology introduced from PCIe 6.0, which allows encoding two data bits per clock cycle, effectively improving data transmission efficiency.
3. Pay attention to channel parameters and accessibility:
In the design, attention should be paid to the channel performance of the physical layer to ensure the integrity of signals over longer distances, which is particularly important for the interconnection within data centers.
4. Continuously provide low latency and high reliability:
Ensuring that data transmission is not only fast, but also has extremely low latency and high reliability is crucial for real-time applications such as artificial intelligence/machine learning (AI/ML) and cloud computing.
5. Improve energy efficiency:
With the enhancement of device performance, energy efficiency issues have become increasingly critical. PCIe 7.0 is committed to reducing energy consumption, making data centers and other high-performance computing environments more environmentally friendly and economical.
6. Maintain backward compatibility:
Despite the introduction of many new technologies, PCIe 7.0 still supports all previous versions of PCIe technology, which means existing hardware investments can be protected while smoothly transitioning to the new generation standards.
